Synchronous high speed serial interfaces typically require the clock and data to be sent from the transmitting device to the receiving device as phase aligned paired data. If the clock and data are not paired together the resulting phase relationship is difficult to predict and can vary over temperature. The problem is greatly exacerbated if the clock and data paths each use either a different number of buffers, buffer component types, or system routing topology. To overcome the data/clock skew over temperature, high data rate serial interfaces must be resynchronized periodically over temperature in order to compensate for the changing skew. Unfortunately, during this resynchronization, the data is interrupted by a synchronization pattern. Alternatively, the interface could be treated asynchronously and a device with clock recovery circuitry could be implemented. However, such a set up increases both the cost and the complexity of the interface.